The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a method of forming a non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by providing a semiconductor diffusion barrier layer and a semiconductor punch through stop layer directly beneath each semiconductor fin.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (finFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
10 nm and beyond technology is looking to provide semiconductor fins from a bulk silicon substrate rather than from a semiconductor-on-insulator (SOI) substrate since SOI substrates are more expensive than their bulk semiconductor counterparts. For bulk semiconductor fins, there is a need to isolate the bottommost surface of each semiconductor fin from a remaining portion of the bulk silicon substrate.